Logic Systems N2 — Document

April 2018 — N2 — Logic Systems

N2 2018 Nated Engineering
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🎯 100 marks ⏱️ 3h 📄 6 pages 📝 47 items found 📚 1 topics 🔑 1 key info
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Questions — A Preview of What to Expect in the Document

47
This section provides a quick preview of questions from the document. It may not display every question or the complete wording of each one. For the full content, including diagrams, tables and other information, view the original PDF above.
Q1— Section header —
1.1Various options are given as possible answers to the following questions. Choose the answer and write only the letter (A D\ next to the question number (1.1.1
1.1.10\in the ANSWER BOOK.
1.1.1NOT gate is also known as converter
1.1.2Besides NAND gate , a universal gate is a/an
1.1.3A group of binary cells Counter Register Latch
1.1.4The most basic arithmetic functio n: Addition Subtraction Multiplication
1.1.5Dec imal number 4 in excess 3 code
1.1.6Full 2 bits 3 bits
1.1.7Flip lops can be constructed with two
1.1.8The difference between flip flops lies in their
1.1.9The state of flip flop can be switched by changing
1.1.10ogic gates take inp ut signals and generate signals within gate
1.2Indicate whether the following statements are TRUE or FALSE. Choose the answer and write only 'true' or 'false' next to the question number (1.2.1
1.2.5\ the ANSWER BOOK.
1.2.1A T type flip flop is constructed by connecting an inverter between the set and the clock terminals.
1.2.2ROMs are volatile.
1.2.3An output of an exclusive OR (XOR\gate is 1 only when the inputs are different.
1.2.4Bidirectional shift registers can shift data either right or left.
1.2.515
Q2— Section header —
2.1List FOUR binary subtraction rules. (4\
2.2Convert the following binary numbers to their equivalent decimal numbers:
2.2.1111000
2.2.2
2.3Convert the following decimal numbers to their equivalent binary numbers:
2.3.127 10
2.3.2
2.4
2.5Explain 2421 BCD code. (3\
2.6Decode the XS3 number 101110101000 to its decimal equivalent. (4\
2.7Draw a complete, labelled diagra m of a full adder made of NAND gates. Clearly show ALL inputs and outputs. (8\ [35]35
Q3— Section header —
3.1X and Y are two switches connected in parallel and this combination is then connected in series with the load LED and source battery. When both switches are open, the current does not flow to LED, but when any switch is
3.1.1What type of gate is defined by this description? (2\
3.1.2Draw the truth table and the IEC symbol for the circuit (6\ (8080262\ T920
3.2Study FIGURE 1 and answer the questions: FIGURE 1
3.2.1Wh ich type of flip flop is represented in FIGURE 1 (2\
3.2.2Draw the truth table for the flip
Q3— Section header —
3.2.3Draw the logic circuit for the IEC symbol in FIGURE 1 (10\
3.3Name the IEC symbol shown in FIGURE 2 FIGURE 2 (2\ [25]25
Q4— Section header —
4.1Draw a fully labelled circuit diagram of a left shift register using D type flip flops with the following features: parallel input, series. (9\
4.2Draw the truth table of a four bit decade up counter. (5\
4.3Draw a fully labelled circuit diagram of a ri ght shift register using D type flip flops with the following features: series input, parallel output and series
4.4Differentiate between a series in series out shift register and a

Topics Identified

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Business Plan

Mark Allocation

Total100 marks
Sections15 + 35 + 25 + 25 = 100 marks

Key Information

Contact Number0111010100

Paper information

TitleDocument
SubjectLogic Systems
LevelN2
Document typeQuestion paper
Year2018
MonthApril
Pages6
Downloads2

Examination context

Decade2010s
Years ago8y
SeasonAutumn (SH)
Start daySunday
Exam periodApril 2018
Days since exam3,116

About Logic Systems examination preparation

This TVET examination resource can be used as part of a structured revision programme. Past papers are most useful when learners attempt questions independently, work within a realistic time limit, and review their answers afterwards.

How to use this resource for revision

A TVET past examination paper is most useful when it is treated as an active revision exercise. Try the questions yourself before checking the corresponding memorandum. Where you make an error, identify the reason — was it a knowledge gap, a calculation mistake, an interpretation issue, or an examination technique problem?

For stronger examination practice, complete the paper without unnecessary interruptions and keep track of the questions that take the most time. Afterwards, review the memorandum and separate knowledge gaps from mistakes caused by interpretation, calculation, structure, or examination technique.

understanding question requirements
applying subject knowledge
working under time constraints
checking answers
identifying revision priorities

A practical revision approach

Start by completing the resource without looking at the memorandum. Review incorrect and incomplete answers afterwards and make a short revision list based on the areas that caused difficulty.

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